Y2B-215 — Describe the researched CPU0 first-boot hardware
> **Historical record.** The dates, candidate identity, "current" claims, > next steps and permissions below belong to this recorded boundary. See > [current state](../../CURRENT_PLATFORM_STATE.md) for the latest physically observed result.Depends on Y2B-210 (#10), D08/D09. Offline only.
Create a minimal Y2 DTS from the audited upstream MT6582 CPU/GIC/sysirq/GPT and fixed-clock descriptions. Preserve provenance. Include only CPU0 and the package-default UART3 diagnostic candidate; omit unrelated peripherals. No guessed pinctrl, DMA channels, storage or reserved-memory expansion.
Acceptance:
- Exactly D08's two memory banks and permanent 16 KiB FDT reservation.
- initrd end derived later from actual gzip bytes; no placeholder may reach a final DTB.
- Single CPU, confirmed interrupt/clock addresses; no HYP/PSCI or unresearched device nodes.
- Controlled bootargs, stdout-path without early baud override; U10a explicitly remains a launch gate.
- Compile DTS syntax using a bounded test initrd length; final DTB requires the real initramfs and independent decoding.
Validation: upstream v6.18 dtc compiled the DTS without warnings using the explicitly test-only 0x1000 initrd length. Final DTB is rebuilt from the actual gzip length; this syntax-check DTB is not an accepted artifact. GIC virtualization register windows are omitted because only CPU0 distributor/CPU-interface operation is selected.
Historical checkpoint: Y2E-140 (#16) later supersedes the initial UART3 choice with installed-evidence UART0/IRQ51 (D10), rebuilding and revalidating the whole artifact. This completed issue remains the original implementation history.